Services

Superion has a team of highly-experienced senior design engineers that perform the logic design and RTL implementation. Many years of complex ASIC development experience provides our team with the ability to create innovative and efficient design solutions that meet design requirements.

Drawing from expertise that spans across multiple domains, our team brings a broad array of techniques and strategies to the logic design and coding process. This allows us to adapt and apply the expertise and approach from prior experiences to virtually any type of problem.

RTL coding is done using Verilog and SystemVerilog leveraging the power of SystemVerilog constructs to maximize design modularity, flexibility and partitioning. At the same time, care is taken to ensure that implemented code will be compatible with current versions of CAD tools and development methodologies.

Our design team is very disciplined in the use of assertions and cover properties as part of the design flow. This practice is a key contributor to the design approach employed at Superion. Embedded assertions and cover properties written by the designers directly contributes to the robustness of the verification process and also positions the designs for formal property checking simulations.

The design verification (DV) team at Superion stays on the leading edge of advanced verification techniques, technologies and methodologies. Like our design team, our DV group is comprised of senior semiconductor verification professionals that have a passion for focused and determined pursuit of functional verification.

For nearly 20 years, our team has approached the verification process with randomized stimulus, self-checking test environments, and modular testbench partitioning. This approach resulted in the most effective isolation of key functionality and top-level chip validation.

Now, with advanced Hardware Verification Languages (HVLs) and methodologies such as the Universal Verification Methodology (UVM), our teams can fully utilize very powerful verification constructs and practices that are being actively developed, supported and enhanced by the greater verification community. Furthermore, our experience with multiple EDA vendors allows us to easily adapt to customer-preferred environments and tool flows.

Our specific experience using Formal Modeling Analysis and Formal Property Checking gives us an edge for designs where functional simulation alone may not provide the robustness and rigor required to ensure a defect free design result.

At Superion Technology, synthesis is performed by the logic designer that is crafting the RTL for a given block. Putting synthesis in the hands of the designer provides the ability to validate implementation goals by allowing real-time synthesis results to inform the ongoing design activity.

As part of the physically-aware approach used by our team for design development, we typically leverage physical synthesis tools to generate the netlists that are delivered into the physical design flow.

Though Static Timing Analysis is most often associated with the physical design phase of a development project, Superion tries to provide early timing analysis as part of logic design activities.

This starts early when timing constraints are developed and checked during early synthesis explorations. These constraints are updated to reflect physical design progress as the project progresses and provide the coupling between logic development and physical implementation. Detailed knowledge and hands-on experience with the timing constraints creates a more efficient review loop between designers and STA engineers during the timing closure process.